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AD73511 a rev. pra 08/99 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. one technology way, p .o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 world wide web site: http://www.analog.com fax: 781/326-8703 analog devices, inc., 1998 low-power cmos analog front end with flash based dsp microcomputer preliminary technical data preliminary technical data features afe performance 16-bit a/d converter 16-bit d/a converter programmable input/output sample rates 77 db adc snr 77 db dac snr 64 ks/s maximum sample rate C90 db crosstalk low group delay (25 m m m m m s typ per adc channel, 50 m m m m m s typ per dac channel) programmable input/output gain on-chip reference dsp performance 19 ns instruction cycle time @ 3.3 volts, 52 mips sustained performance AD73511-80 80k bytes of on-chip ram, configured as 16k words program memory ram and 16k words data memory ram AD73511-40 40k bytes of on-chip ram, configured as 8k words program memory ram and 8k words data memory ram flash memory 64 kbytes writable in pages of 128 bytes fast page write cycle of 5 ms (typical) general description the AD73511 is a single-device incorporating a single analog front end, microcomputer optimized for digital signal processing (dsp) and a flash based boot memory for the dsp. the AD73511s analog front end (afe) section is suitable for general purpose applications including speech and telephony. the afe section features a 16-bit a/d converter and a 16-bit d/a converter. each converter provides 77 db signal-to-noise ratio over a voiceband signal bandwidth. the AD73511 is particularly suitable for a variety of applica- tions in the speech and telephony area including low bit rate, high quality compression, speech enhancement, recognition and synthesis. the low group delay characteristic of the afe makes it suitable for single or multichannel active control applications. the a/d and d/a conversion channels feature programmable input/ouput gains with ranges 38 db and 21 db respectively. an on-chip reference voltage is included to allow single supply operation. functional block diagram the sampling rate of the afe is programmable with four separate settings offering 64, 32, 16 and 8 khz sampling rates (from a master clock of 16.384 mhz) while the serial port (sport2) allows easy expansion of the number of i/o channels by cascading extra afes external to the AD73511. the AD73511s dsp engine combines the adsp-2100 family base architecture (three computational units, data address generators and a program sequencer) with two serial ports, a 16-bit internal dma port, a byte dma port, a programmable timer, flag i/o, extensive interrupt capabilities and on-chip program and data memory. the AD73511-80 integrates 80k bytes of on-chip memory configured as 16k words (24-bit) of program ram, and 16k words (16-bit) of data ram. the AD73511-40 integrates 40k bytes of on-chip memory configured as 8k words (24- bit) of program ram, and 8k words (16-bit) of data ram. both devices feature a flash memory array of 64 kbytes (512 kbits) connected to the dsps byte-wide dma port (bdma). this allows non-volatile storage of the dsps boot code and system data parameters. power-down circuitry is also provided to meet the low power needs of battery operated portable equipment. the AD73511 is available in a 119-ball pbga package. adc dac external address bus byte dma controller external data bus full memory mode serial ports sport 0 shifter mac alu arithmetic units memory programmable i/o and flags timer adsp-2100 base architecture power-down control program sequencer dag 2 data address generators program memory address data memory address program memory data data memory data dag 1 16k dm (optional 8k) 16k pm (optional 8k) sport 1 serial port sport 2 ref analog front end section flash memory 64 kbytes
AD73511 C2C rev. pra 08/99 preliminary technical data preliminary technical data architecture overview the AD73511 instruction set provides flexible data moves and multifunction (one or two data moves with a computation) instructions. every instruction can be executed in a single processor cycle. the AD73511 assembly language uses an algebraic syntax for ease of coding and readability. a comprehensive set of development tools supports program development. adc dac external address bus byte dma controller external data bus full memory mode serial ports sport 0 shifter mac alu arithmetic units memory programmable i/o and flags timer adsp-2100 base architecture power-down control program sequencer dag 2 data address generators program memory address data memory address program memory data data memory data dag 1 16k dm (optional 8k) 16k pm (optional 8k) sport 1 serial port sport 2 ref analog front end section flash memory 64 kbytes figure 1. functional block diagram figure 1 is an overall block diagram of the AD73511. the processor section contains three independent computational units: the alu, the multiplier/accumulator (mac) and the shifter. the computational units process 16-bit data directly and have provisions to support multiprecision computations. the alu performs a standard set of arithmetic and logic operations; division primitives are also supported. the mac performs single-cycle multiply, multiply/add and multiply/ subtract operations with 40 bits of accumulation. the shifter performs logical and arithmetic shifts, normalization, denormalization and derive exponent operations. the internal result (r) bus connects the computational units so that the output of any unit may be the input of any unit on the next cycle. a powerful program sequencer and two dedicated data address generators ensure efficient delivery of operands to these compu- tational units. the sequencer supports conditional jumps, sub- routine calls and returns in a single cycle. with internal loop counters and loop stacks, the AD73511 executes looped code with zero overhead; no explicit jump instructions are required to maintain loops. two data address generators (dags) provide addresses for simultaneous dual operand fetches (from data memory and program memory). each dag maintains and updates four address pointers. whenever the pointer is used to access data (indirect addressing), it is post-modified by the value of one of four possible modify registers. a length value may be associated with each pointer to implement automatic modulo addressing for circular buffers. the two address buses (pma and dma) share a single external address bus, allowing memory to be expanded off- chip, and the two data buses (pmd and dmd) share a single external data bus. byte memory space and i/o memory space also share the external buses. an interface to low cost byte-wide memory is provided by the byte dma port (bdma port). the bdma port is bidirectional and can directly address up to four megabytes of external ram or rom for off-chip storage of program overlays or data tables. the AD73511 can respond to eleven interrupts. there can be up to six external interrupts (one edge-sensitive, two level- sensitive and three configurable) and seven internal interrupts generated by the timer, the serial ports (sports), the byte dma port and the power-down circuitry. there is also a master reset signal. the two serial ports provide a complete synchronous serial interface with optional companding in hardware and a wide variety of framed or frameless data transmit and receive modes of operation. each port can generate an internal programmable serial clock or accept an external serial clock. the AD73511 provides up to 13 general-purpose flag pins. the data input and output pins on sport1 can be alternatively configured as an input flag and an output flag. in addition, there are eight flags that are programmable as inputs or outputs and three flags that are always outputs. a programmable interval timer generates periodic interrupts. a 16-bit count register (tcount) is decremented every n processor cycle, where n is a scaling value stored in an 8-bit register (tscale). when the value of the count register reaches zero, an interrupt is generated and the count register is reloaded from a 16-bit period register (tperiod).
AD73511 C3C rev. pra 08/99 preliminary technical data preliminary technical data analog front end the afe section is configured as a separate block which is normally connected to either sport0 or sport1 of the dsp section. as it is not hard-wired to either sport the user has total flexibility in how they wish to allocate system resources to support the afe. it is also possible to further expand the number of analog i/o channels connected to the sport by cascading other single or dual channel afes (ad73311 or ad73322) external to the AD73511. the afe is configured as a single i/o channel (similar to that of the discrete ad73311l - refer to the ad73311l datasheet for more details) having a 16-bit sigma-delta based adc and dac. both adc and dac share a common reference whose nominal value is 1.2v. figure 2 shows a block diagram of the afe section of the AD73511. it shows an adc and dac as well as a common reference. communication to both channels is handled by the sport2 block which interfaces to either sport0 or sport1 of the dsp section. figure 2: functional block diagram of analog front end section agnd1 agnd2 dgnd dvdd avdd2 avdd1 vinp vinn voutp voutn refcap refout sdi sdifs sclk sdo sdofs se mclk reset 1-bit dac reference serial i/o port interpolator decimator switched- capacitor low-pass filter continuous time low-pass filter +6/-15db pga 0/38db pga analog sigma-delta modulator digital sigma-delta modulator ad73311l analog loopback/ single- ended enable the i/o channel features fully differential inputs and outputs. the input section allows direct connection to the internal programmable gain amplifier at the input of the sigma-delta adc section. the input section also features programmable differential channel inversion and configuration of the the differential input as two separate single-ended inputs. the adc features a second order sigma- delta modulator which samples at mclk/8. its bitstream output is filtered and decimated by a sinc-cubed decimator to provide a sample rate selectable from 64 khz, 32 khz, 16 khz or 8 khz (based on an mclk of 16.384 mhz). the dac channel features a sinc-cubed interpolator which increases the sample rate from the selected rate to the digital sigma-delta modulator rate of mclk/8. the digital sigma- delta modulators output bit-stream is fed to a single-bit dac whose output is reconstructed/filtered by two stages of low- pass filtering (switched capacitor and continuous time) before being applied to the differential output driver.
C4C rev. pra 08/99 AD73511Cspecifications preliminary technical data (avdd = dvdd = +3.0v to 3.6v; dgnd = agnd = 0 v, f mclk = 16.384 mhz, f samp = 64 khz; t a = t min to t max , unless otherwise noted) parameter min typ max units test conditions afe section reference refcap absolute voltage, v refcap 1.08 1.2 1.32 v refcap tc 50 ppm/c 0.1 f capacitor required from refout refcap to agnd2 typical output impedance 145 w absolute voltage, v refout 1.08 1.2 1.32 v unloaded minimum load resistance 1 k w maximum load capacitance 100 pf adc specifications maximum input range at vin 2, 3 1.578 v p-p measured differentially. C2.85 dbm max. input = (1.578/1.2)*v refcap nominal reference level at vin 1.0954 v p-p measured differentially (0 dbm0) C6.02 dbm absolute gain pga = 0 db C2.2 -0.6 +1.0 db 1.0 khz, 0 dbm0 pga = 38 db C1.0 db 1.0 khz, 0 dbm0 gain tracking error 0.1 db 1.0 khz, +3 dbm0 to C50 dbm0 signal to (noise + distortion) refer to figure 5 pga = 0 db 70 76 db 300 hz to 3400 hz; 70 74 db 0 hz to f samp /2; 72 db 300 hz to 3400 hz; f samp = 64 khz 56 db 0 hz to f samp /2; f samp = 64 khz pga = 38 db 60 db 300 hz to 3400 hz; 59 db 0 hz to f samp /2 total harmonic distortion pga = 0 db C85 C70 db 300 hz to 3400 hz; pga = 38 db C85 db 300 hz to 3400 hz; intermodulation distortion C82 db pga = 0 db idle channel noise C76 dbm0 pga = 0 db crosstalk C100 db adc input level: 1.0khz, 0 dbm0 dac input at idle dc offset C20 +2 +25 mv pga = 0 db power supply rejection C84 db input signal level at avdd and dvdd pins: 1.0 khz, 100 mv p-p sine wave group delay 4, 5 25 s f samp = 64 khz input resistance at pga 2, 4, 6 45 k w dmclk = 16.384 mhz dac specifications maximum voltage output swing 2 single ended 1.578 v p-p pga = 6 db C2.85 dbm max. output = (1.578/1.2)*v refcap differential 3.156 v p-p pga = 6 db 3.17 dbm max. output = 2*((1.578/1.2)*v refcap ) nominal voltage output swing (0 dbm0) single-ended 1.0954 v p-p pga = 6 db C6.02 dbm differential 2.1909 v p-p pga = 6 db 0 dbm output bias voltage 1.08 1.2 1.32 v refout unloaded absolute gain C1.8 -0.7 +0.4 db 1.0 khz, 0 dbm0; unloaded gain tracking error 0.1 db 1.0 khz, +3 dbm0 to C50 dbm0 signal to (noise + distortion) at 0 dbm0 pga = 0 db 70 77 db 300 hz to 3400 hz 76 db 300 hz to 3400 hz; f samp = 64 khz pga = 6 db 77 db 300 hz to 3400 hz; 77 db 300 hz to 3400 hz; f samp = 64 khz
C5C rev. pra 08/99 AD73511 preliminary technical data preliminary technical data parameter min typ max units test conditions (style: table col.head) total harmonic distortion at 0 dbm0 pga = 0 db -80 C70 db pga = 6 db -80 db intermodulation distortion C85 db pga = 0 db idle channel noise C76 dbm0 pga = 0 db crosstalk C100 db adc input level: agnd; dac output level: 1.0 khz, 0 dbm0 power supply rejection C81 db input signal level at avdd and dvdd pins: 1.0 khz, 100 mv p-p sine wave group delay 4, 5 25 s f samp = 64 khz; interpolator bypassed 50 s f samp = 64 khz output dc offset 2, 7 C30 +5 +50 mv pga = 6 db minimum load resistance, r l 2, 8 single-ended 4 150 w differential 150 w maximum load capacitance, c l 2, 8 single-ended 4 500 pf differential 100 pf logic inputs v inh , input high voltage dvdd C 0.8 dvdd v v inl , input low voltage 0 0.8 v i ih , input current -10 +10 a c in , input capacitance 10 pf logic output v oh , output high voltage dvdd C 0.4 dvdd v |iout| - 100 a v ol , output low voltage 0 0.4 v |iout| - 100 a three-state leakage current C10 +10 a power supplies avdd1, avdd2 3.0 3.6 v dvdd 3.0 3.6 v i dd 10 see table i notes 1 operating temperature range is as follows: C20c to +85c. therefore, t min = C20c and t max = +85c. 2 test conditions: input pga set for 0 db gain, output pga set for 6 db gain, no load on analog outputs (unless otherwise noted). 3 at input to sigma-delta modulator of adc. 4 guaranteed by design. 5 overall group delay will be affected by the sample rate and the external digital filtering. 6 the adcs input impedance is inversely proportional to dmclk and is approximated by: (3.3 * 10 11 )/dmclk. 7 between voutp1 and voutn1 or between voutp2 and voutn2. 8 at vout output. 9 frequency responses of adc and dac measured with input at audio reference level (the input level that produces an output level of C10 dbm0), with 38 db preamplifier bypassed and input gain of 0 db. 10 test conditions: no load on digital inputs, analog inputs ac coupled to ground, no load on analog outputs. specifications subject to change without notice.
C6C rev. pra 08/99 AD73511Cspecifications preliminary technical data (avdd = dvdd = +3.0v to 3.6v; dgnd = agnd = 0 v, f mclk = 16.384 mhz, f samp = 64 khz; t a = t min to t max , unless otherwise noted) parameter test conditions min typ max unit dsp section v ih hi-level input voltage 1, 2 @ v dd = max 2.0 v v ih hi-level clkin voltage @ v dd = max 2.2 v v il lo-level input voltage 1, 3 @ v dd = min 0.8 v v oh hi-level output voltage 1, 4, 5 @ v dd = min i oh = C0.5 ma 2.4 v @ v dd = min i oh = C100 a 6 v dd C 0.3 v v ol lo-level output voltage 1, 4, 5 @ v dd = min i ol = 2 ma 0.4 v i ih hi-level input current 3 @ v dd = max v in = v dd max 10 a i il lo-level input current 3 @ v dd = max v in = 0 v 10 a i ozh three-state leakage current 7 @ v dd = max v in = v dd max 8 10 a i ozl three-state leakage current 7 @ v dd = max v in = 0 v 8 10 a i dd supply current (idle) 9 @ v dd = 3.3 t ck = 19 ns 10 10 ma t ck = 25 ns 10 8ma t ck = 30 ns 10 7ma i dd supply current (dynamic) 11 @ v dd = 3.3 t amb = +25c t ck = 19 ns 10 51 ma t ck = 25 ns 10 41 ma t ck = 30 ns 10 34 ma c i input pin capacitance 3, 6, 12 @ v in = 2.5 v f in = 1.0 mhz t amb = +25c 8 pf c o output pin capacitance 6, 7, 12, 13 @ v in = 2.5 v f in = 1.0 mhz t amb = +25c 8 pf notes 1 1 bidirectional pins: d0Cd23, rfs0, rfs1, sclk0, sclk1, tfs0, tfs1, a1Ca13, pf0Cpf7. 1 2 input only pins: reset, br, dr0, dr1, pwd. 1 3 input only pins: clkin, reset, br, dr0, dr1, pwd. 1 4 output pins: bg, pms, dms, bms, ioms, cms, rd, wr, pwdack, a0, dt0, dt1, clkout, fl2C0, bgh. 1 5 although specified for ttl outputs, all AD73511 outputs are cmos-compatible and will drive to v dd and gnd, assuming no dc loads. 1 6 guaranteed but not tested. 1 7 three-statable pins: a0Ca13, d0Cd23, pms, dms, bms, ioms, cms, rd, wr, dt0, dt1, sclk0, sclk1, tfs0, tfs1, rfs0, rfs1, pf0Cpf7. 1 8 0 v on br. 1 9 idle refers to AD73511 state of operation during execution of idle instruction. deasserted pins are driven to either v dd or gnd. 10 v in = 0 v and 3 v. for typical figures for supply currents, refer to power dissipation section. 11 i dd measurement taken with all instructions executing from internal memory. 50% of the instructions are multifunction (types 1, 4, 5, 12, 13, 14), 30% are type 2 and type 6, and 20% are idle instructions. 12 applies to pbga package type. 13 output pin capacitance is the capacitive load for any three-stated output pin. specifications subject to change without notice.
C7C rev. pra 08/99 AD73511 preliminary technical data preliminary technical data power consumption conditions typ. max. se mclk on test conditions afe section adc on only 7 7.2 1 yes refout disabled adc and dac on 11 12 1 yes refout disabled refcap on only 0.65 1.00 0 no refout disabled refcap and 2.7 3.8 0 no refout on only all afe sections off 0.6 0.65 0 yes mclk active levels equal to 0v and dvdd all afe sections off 2 a 10 a 0 no digital inputs static and equal to 0 v or dvdd dsp section idle mode 6.4 - - dynamic 43 - - the above values are in ma and are typical values unless otherwise noted. timing characteristics - afe section parameter limit units description clock signals see figure 1 t 1 61 ns min 16.384 mhz mclk period t 2 24.4 ns min mclk width high t 3 24.4 ns min mclk width low serial port see figures 3 and 4 t 4 t 1 ns min sclk period (sclk = mclk) t 5 0.4 * t 1 ns min sclk width high t 6 0.4 * t 1 ns min sclk width low t 7 20 ns min sdi/sdifs setup before sclk low t 8 0 ns min sdi/sdifs hold after sclk low t 9 10 ns max sdofs delay from sclk high t 10 10 ns min sdofs hold after sclk high t 11 10 ns min sdo hold after sclk high t 12 10 ns max sdo delay from sclk high t 13 30 ns max sclk delay from mclk
AD73511 C8C rev. pra 08/99 preliminary technical data preliminary technical data ordering guide temperature package package model range description option AD73511bb-80 -20 c to +85 c 119-ball plastic ball grid array b-119 AD73511bb-40 -20 c to +85 c 119-ball plastic ball grid array b-119 caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the AD73511 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. pbga ball configuration 6 12345 7 irqe / pf4 dms vdd (int) clkin a11/ iad10 a7/ iad6 a4/iad3 irql0 / pf5 pms w r xtal a12 / iad11 a8/iad7 a5/iad4 irql1 / pf6 ioms rd vdd (ext) a13 / iad12 a9/iad8 gnd irq2 / pf7 cms bms clkout gnd a10 / iad9 a6/ iad5 dt0 tfs0 rfs0 a3/iad2 a2/iad1 a1/ iad0 a0 dr0 sclk0 dt1/f0 pwdack bgh mode a / pf0 mode b/pf1 tfs1/ irq1 rfs1/ irq0 dr1/fi gnd pwd vdd (ext) mode c/ pf2 sclk1 ereset reset pf3 fl0 fl1 fl2 ems ee eclk d23 d22 d21 d20 elout elin eint d19 d18 d17 d16 bg d3 / iack d5/ial d8 d9 d12 d15 ebg d2 / iad15 d4 / is d7/ iwr vdd (ext) d11 d14 br d1/ iad14 vdd (int) d6 / ird gnd d10 d13 ebr d0 / iad13 dvdd dgnd areset sclk2 amclk sdo sdofs sdifs sdi se refcap refout vinp nc vinn nc nc nc nc agnd avdd nc nc voutp voutn nc a b c d e f g h j k l m n p r t u top view notes: vdd (int) - dsp core supply vdd (ext) - dsp i/o driver supply both vdd (int) and vdd (ext) should be powered from the same supply.
AD73511 C9C rev. pra 08/99 preliminary technical data preliminary technical data pin function description mnemonic function vinp analog input to the positive terminal of the input channel. vinn analog input to the negative terminal of the input channel. refout buffered reference output, which has a nominal value of 1.2 v. refcap a bypass capacitor to agnd2 of 0.1 f is required for the on-chip reference. the capacitor should be fixed to this pin. avdd2 analog power supply connection for codec 2. agnd2 analog ground/substrate connection for codec 2. dgnd digital ground/substrate connection. dvdd digital power supply connection. areset active low reset signal. this input resets the entire chip, resetting the control registers and clearing the digital circuitry. sclk output serial clock whose rate determines the serial transfer rate to/from the codec. it is used to clock data or control information to and from the serial port (sport). the frequency of sclk is equal to the frequency of the master clock (mclk) divided by an integer numberthis integer number being the product of the external master clock rate divider and the serial clock rate divider. mclk master clock input. mclk is driven from an external clock signal. sdo serial data output of the codec. both data and control information may be output on this pin and is clocked on the positive edge of sclk. sdo is in three-state when no information is being transmitted and when se is low. sdofs framing signal output for sdo serial transfers. the frame sync is one-bit wide and it is active one sclk period before the first bit (msb) of each output word. sdofs is referenced to the positive edge of sclk. sdofs is in three-state when se is low. sdifs framing signal input for sdi serial transfers. the frame sync is one-bit wide and it is valid one sclk period before the first bit (msb) of each input word. sdifs is sampled on the negative edge of sclk and is ignored when se is low. sdi serial data input of the codec. both data and control information may be input on this pin and are clocked on the negative edge of sclk. sdi is ignored when se is low. se sport enable. asynchronous input enable pin for the sport. when se is set low by the dsp, the output pins of the sport are three-stated and the input pins are ignored. sclk is also disabled internally in order to decrease power dissipation. when se is brought high, the control and data registers of the sport are at their original values (before se was brought low), however the timing counters and other internal registers are at their reset values. agnd1 analog ground/substrate connection for codec 1. avdd1 analog power supply connection for codec 1. reset (input) processor reset input br (input) bus request input bg (output) bus grant output bgh (output) bus grant hung output dms (output) data memory select output pms (output) program memory select output ioms (output) memory select output bms (output) byte memory select output cms (output) combined memory select output rd (output) memory read enable output wr (output) memory write enable output irq2 / (input) edge- or level-sensitive interrupt pf7 (input/output) request. 1 programmable i/o pin irql0 / (input) level-sensitive interrupt requests 1 pf6 (input/output) programmable i/o pin irql1 / (input) level-sensitive interrupt requests 1 pf5 (input/output) programmable i/o pin irqe / (input) edge-sensitive interrupt requests 1 pf4 (input/output) programmable i/o pin mode d/ (input) mode select inputchecked only during reset pf3 (input/output) programmable i/o pin during normal operation mode c/ (input) mode select inputchecked only during reset pf2 (input/output) programmable i/o pin during normal operation mode b/ (input) mode select inputchecked only during reset pf1 (input/output) programmable i/o pin during normal operation
AD73511 C10C rev. pra 08/99 preliminary technical data preliminary technical data mode a/ (input) mode select inputchecked only during reset pf0 (input/output) programmable i/o pin during normal operation clkin, xtal (inputs) clock or quartz crystal input clkout (output) processor clock output sport0 (inputs/outputs) serial port i/o pins sport1 (inputs/outputs) serial port i/o pins irq1:0 (inputs) edge- or level-sensitive interrupts, fi (input) flag in 2 fo (output) flag out 2 pwd (input) power-down control input pwdack (output) power-down control output fl0, fl1, fl2 (outputs) output flags vdd and gnd power and ground ez-port (inputs/outputs) for emulation use
AD73511 C11C rev. pra 08/99 preliminary technical data preliminary technical data
AD73511 C12C rev. pra 08/ printed in u.s.a. 00000000 outline dimensions dimensions shown in inches and (mm). preliminary technical data preliminary technical data a b c d e f g h j k l m n p r t u 7 6 5 4 3 2 1 0.050 (1.27) bsc 0.800 (20.32) bsc 0.300 (7.62) bsc 0.050 (1.27) bsc 0.126 (3.19) ref 0.033 (0.84) ref bottom view a1 top view 0.874 (22.20) 0.858 (21.80) 0.559 (14.20) 0.543 (13.80) 0.089 (2.27) 0.073 (1.85) detail a seating plane 0.037 (0.95) 0.033 (0.85) 0.028 (0.70) 0.020 (0.50) detail a 0.035 (0.90) 0.024 (0.60) ball diameter 0.022 (0.56) ref

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